The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches.Ī flexible, bidirectional 20-bit I/O bus accommodates a variety of custom digital back ends or open market DSPs. The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market. Three auxiliary converters are also available to provide required system level control voltages or to monitor system signals. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2× or 4× interpolation filter. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. Two speed grades are available, -50 and -80. The AD9861 integrates dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC ®). The AD9861 is a member of the MxFE family-a group of integrated converters for the communications market.
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The 4D4AC model supports the full instantaneous channel bandwidth, whereas the 4D4AB model supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also has an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications. The device features eight transmit and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards.
The AD9081 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The AD9081 mixed signal front end (MxFE ®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. Electronic test and measurement systems.Phased array radar and electronic warfare.Microwave point-to-point, E-band and 5G mmWave.The 2D2AC model supports two DACs and two ADCs. The 4D2AC model supports four DACs and two ADCs.
The device also features low latency loopback, frequency hopping modes, and datapath multiplexer (mux) configurations useful for phase array radar system and electronic warfare applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204B/C data transceiver port. The device also has an on-chip clock multiplier and digital signal processing (DSP) capability targeted at either wideband or multiband, direct to RF applications.
The device features eight transmit lanes and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The AD9082 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instantaneous bandwidth. The AD9082 mixed signal front-end (MxFE ®) is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) core, and 12-bit, 6 GSPS maximum sample rate, RF analog-to-digital converter (ADC) cores. Integrated digital signal processing supports the transition to software-defined radio platforms, creating a highly configurable, common hardware/software platform that can be used in multiple applications across a broad array of end markets. This allows for the elimination of discrete data converters and traditional RF front-end components to reduce size, weight, power, and cost. MxFEs from Analog Devices offer smart integration of RF analog-to-digital converters (ADC), RF digital-to-analog converters (DAC), on-chip digital signal processing, and clock/PLL for multichip synchronization. This solves several complex challenges including increasing bandwidth demands and signal chain complexity as system operation moves from the RF to the mmWave spectrum domain and as bandwidth demands move from megahertz to gigahertz. The mixed-signal front end (MxFE®) provides today’s system designers working in communication infrastructure, instrumentation, and aerospace and defense with a scalable software-designed radio solution with a very wide 7.5 GHz bandwidth. Scalable Software-Defined Radio Solution with 7.5 GHz Bandwidth
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